The next program will be held in the summer of 2010

Please scroll down the page for abstracts and bios from the 2008 program

Abstract: Interconnect Reliability
Electromigration induced damage, which is in principal an irreversible mass diffusion under high current density, has been a concern for VLSI design for a long time.  Miniaturization of electronic device sizes down to nano-scale will make electromigration a concern for all conducting components including solder joints.  Thermomigration which is also an irreversible mass transport under high temperature gradient is also a major concern for next generation nanoelectronics and power electronics.  In this lecture basic principles of electromigration and thermomigration in pure metals and solder alloys will be discussed. Lecture will also include experimental results obtained on various test vehicles where electromigration and thermomigration interaction is studied in great detail.

About Dr. Basaran:
Cemal Basaran is Professor and Director of Electronic Packaging Laboratory at the State University of New York at Buffalo, www.packaging.buffalo.edu  He specializes in experimental and computational damage mechanics of Nano and power electronics packaging.  He has authored more than 140 publications in the field of high sensitivity moiré interferometry inspection and thermodynamics based damage mechanics of electronics packaging under electromigration, thermomigration and thermo-mechancal loads.  He holds a MS degree in Civil Engineering from MIT and a PhD in Engineering Mechanics from the University of Arizona in Tucson. He is 1997 recipient of the Department of Defense ONR Young Investigator Award. He is the Assoc. Editor of ASME Journal of Electronic Packaging, IEEE Trans. on Advanced Packaging, the Regional Editor for Americas for Int.  J. of Materials and Structural Integrity and a Member of Editorial Board of Open Civil Engineering Journal and Journal of Recent Patents On Electrical Engineering.

Abstract: The Advanced Technology Program is dead, Long live the Technology Innovation Program.

This presentation will be an overview of the Technology Innovation Program.  It will include a summary of the America Competes Act pointing out the differences between the old ATP legislation and the new TIP legislation.  The presentation will also include a summary of the TIP Rule, fleshing out the TIP legislation, and explaining what the few paragraphs pertaining to TIP mean in the real world.  Finally the presentation will summarize the current TIP competition, how it is being run, and the likely funding and topics that the 2009 competition. 
Though none of the anticipated topics specifically address electronics packaging, many of the proposed projects will rely on new electronic systems with packaging issues.

About Gerald Castellucci:

In 1970, Gerald Castellucci was awarded a Bachelor of Science degree in Electrical Engineering from Virginia Polytechnic Institute and State University, followed by two years of graduate studies in Underwater Acoustics at the Catholic University of America.
He has 42 years of experience in both the public and private sectors.
As an electrical engineer for the Naval Surface Warfare Center he managed large programs including the reduction of acoustic signature of ships and submarines, he designed various transducers, and signal acquisition and processing systems.  At the Naval Sea Systems Command he managed a new weapons program.
In the private sector he designed large electric power converters based on a new family of semiconductors, he invented a short range navigation system based on magnetic fields, and he managed large projects involving the cooperative efforts of Navy organizations, industry, and academia.
Gerald is interested in all aspects of electronics and electric power, including new power semiconductors, fuel cells, photovoltaic systems for village power in the developing world, and new machine technologies.

Abstract: "Harsh Environment/High Temperature"
Sensor and electronic devices capable of operation at high temperatures are required for an integrated vehicle health management (IVHM) system for the next generation of aircraft.  Specifically, 500°C devices are required for real time in situ monitoring and control of next generation aeronautical engines. High temperature sensor and electronic devices can also find applications for long term Venus surface missions and in military, energy, and automobile industries.  Various silicon carbide (SiC) sensors and electronic devices have been demonstrated for operation at 500°C in laboratory conditions.  However, field testing of these devices has been problematic, partially because of the lack of a high temperature durable packaging technology.  Therefore, a compatible packaging technology is needed for both long term testing and applications of these devices.  Prototype high temperature ceramic chip-level packages and printed circuit boards have been developed at NASA Glenn Resea  r!
ch Center.  A ceramic substrate based packaging system has previously been used to facilitate testing of SiC metal-semiconductor-field-effect- transistors (MESFETs) and a high temperature low frequency voltage amplifier based on a SiC transistor at 500°C.  This presentation will summarize the author’s research activity in high temperature packaging, with emphasis on recent studies in packaging substrate materials and the most recent testing results of packaged SiC capacitive pressure sensors and SiC pn-junction-field-effect-transistors (JFETs) based electronics.  A packaged SiC capacitive pressure sensor has been tested up to 500°C, and packaged SiC JFETs ICs have been tested for over 6500 hours at 500°C.

About Dr. Chen:
Liang-Yu Chen received the Ph.D. degree in experimental solid state physics from Case Western Reserve University in 1994.  Currently, he is a senior scientist at Ohio Aerospace Institute/NASA Glenn Research Center.  His research interests include advanced packaging materials, structures, and process for high temperature sensor and electronic devices.

Abstract: "Qualification of a Lead-Free Card Assembly & Test Process for a Server Complexity PCBA"
Since 1999, many OEM companies and their contract manufacturing partners have been converting their product portfolios to comply with EU RoHS regulations.  Significant investment has been made within the electronics industry for the development of new lead-free materials and assembly processes suitable for consumer electronics applications. As a result, the majority of the industry’s material, process, and reliability studies to date have focused on low-to-medium complexity products with only moderate field reliability requirements.

Many firms competing in storage array and server markets continue to take advantage of the “lead in solder” exemption permitted by the EU RoHS directive for these product segments. This exemption allows for the continued use of Pb bearing solder alloys in the manufacture of server and storage array products. The RoHS directive states that reviews will be conducted every four years to assess the continued technical justification for such exemptions. Consistent with this global drive for ever more aggressive environmental stewardship, IBM is actively exploring the limitations of current industry lead-free assembly technology.

This paper describes the process used to qualify a lead-free server complexity PCBA card.  The example described represents entry level server complexity.  It highlights both the successes and technical challenges that remain to produce high reliability, high complexity, lead-free PCBA’s. It outlines the end-to-end lead-free process qualification approach used including a summary of materials compatibility, primary attachment and rework assembly processes, in-circuit and functional test performance, time zero quality assessments, thermal fatigue reliability performance, and mechanical fragility issues.

This work provides a foundation for further material, process and reliability studies that may ultimately enable a range of server products to confidently convert to lead-free card assembly.  With the numerous challenges that remain, continued development is required to ensure quality and reliability for higher complexity products.

About Ms. Cole:
Marie Cole is a Distinguished Engineer in Interconnect Technology Development in the IBM Integrated Supply Chain.  She holds a B.S. in Chemical Engineering from Rensselaer Polytechnic Institute and an M.S. in Materials Science from Columbia University.  For more than 10 years she led IBM's development efforts on CBGA and CCGA packaging.  Recently, she drove the development and implementation of Lead Free packaging and RoHS infrastructure for IBM Microelectronics.  In her current assignment, she is leading the technology development for the conversion of IBM systems to Lead Free soldering.

Abstract:

Thermoelectric cooling (TEC) devices have been around for over thirty years and have been employed in a wide range of cooling applications. However, the physical size and thermal properties of these devices have limited them to niche applications. A new generation of TECs based on thin film thermoelectric materials are being developed that will potentially allow a cooling function to be integrated into a wide range of electronic products. A review of thin film thermoelectric devices and new integration strategies will be presented.

About Philip Deane:

Phil Deane has over twenty years of experience in the development of packaging technology for semiconductor and photonic circuits. Dr. Deane began his carrer AT&T Bell Laboratories where he supported the multichip module business unit and was responsible for new process development, reliability and product qualification and transfer into manufacturing. Most recently at JDS Uniphase, he developed packaging solutions for laser diode and receivers components. Dr. Deane maintains an interest and expertise in solder and solder joint technology. Phil Received his PhD in Physics from the University of North Carolina in 1984.

Abstract: "Realizing Benefits of High Efficiency – High Temperature Devices From a Thermal Management Systems Level Perspective"
There has been, and will continue to be, significant improvements in the capabilities of electronic devices.  Improved efficiency and higher temperature capability are two areas that have benefits directly related to thermal management and the resulting packaging.  On the surface, these benefits appear to be straightforward and relatively simple to realize.  However, system level considerations often complicate the issue and must be considered.  This paper discusses how system level considerations can effect packaging decisions, and thus determine much of the actual benefit the improved devices deliver.

About Dr. Gerstler:
Bill is a Senior Mechanical Engineer in the Thermal Systems Lab (TSL) at GE Global Research.  He leads the Electronics Cooling Lab (a group within TSL) macro/systems group.   During his seven years at GRC, he has worked in the area of rotating electric machine thermal management and thermal management of electronics.  Rotating machine work includes validation testing of GE’s largest air-cooled and hydrogen-cooled generators, various high-speed permanent magnet machines and bearings, and a super-conducting, high-power density generator for the Air Force.  Thermal management of electronics work includes high power density converters and motor controllers.

Prior to joining GE, Bill received his Ph.D. in Mechanical Engineering from the University of Minnesota.  He spent three years with the Department of Energy’s Federal Energy Technology Center’s Coal Preparation Division.  He received his M.S. in Mechanical Engineering from Southern Illinois University, and his Bachelor degree in Physics from Kenyon College.

Abstract: "Synthesis and Applications of Highly Dispersed Uniform Metallic Particles"
The importance of finely divided metals, ranging in size from a few nanometers to several micrometers, is now recognized in many well-established and emerging technological fields. Since these applications are increasingly relying on uniform metallic particles with well-controlled properties, significant research is focused lately on the development of synthetic routes capable of generating such materials.
Chemical precipitation in solutions is one of the oldest, simplest and most versatile methods for preparing highly dispersed metals, as it provides unsurpassed capabilities in fine-tuning the properties of the resulting particles. The presentation will review the mechanisms of the formation of uniform metal colloids in homogeneous solutions and their implications for the design and practical implementation of the precipitation process. The ability to tailor the properties of the metallic particles to present and future specific needs through a proper design and control of the experimental conditions will be discussed and amply illustrated.

About Dr. Goia:
Dr. Dan V. Goia obtained his MS degree from University of Cluj (Romania) and his Ph.D. degree from Clarkson University in 1998. He joined Clarkson University in October 2001, where he presently is a Professor in the Department of Chemistry and the Center for Advanced Materials Processing (CAMP). Prior to his move to Clarkson, Prof. Goia worked for over 20 years in the research organizations of several companies involved in the development and manufacturing of fine particles (pigments, metals, ceramics, etc.) and, until August 2001, he held the position of R&D Director in the Electronic Materials Division of dmc2 Corporation, formerly Degussa Corporation. For the last 20 years, his research has been focused on the development and scale-up of fine and ultra-fine simple and composite metallic particles for electronic, catalytic, and medical applications. Over the last few years he has been particularly interested in the elucidation of the basic mechanisms governing the formation of highly dispersed uniform metallic particles in homogeneous solutions.

Abstract: Powering the Future with NanoTechnology

About Harry Haldar:
Dr. Harry Efstathiadis, Scientist at the Energy & Environmental Technology Applications Center at the College of Nanoscale Science & Engineering.

Abstract: "The US Display Consortium Program on Printed and Flexible Electronics"
Nearly 15 years ago, the US Display Consortium (USDC) was established to help enable the tools, materials, and processes required by the nascent flat panel display industry.  Through a public-private partnership modeled after the Sematech consortium, USDC brought together manufacturers and suppliers, universities, display integrators, and the government to define and implement research and development projects.  Since it’s inception, USDC has initiated over 130 development projects, helping a number of companies to successfully develop important manufacturing tools and novel materials in worldwide use today.

While the USDC continues to maintain a focus in new display technologies, many of the recent USDC programs have focused on two initiatives – flexible displays and printed electronics.  Flexible displays are typically built on plastic films or metal foils rather than rigid glass or silicon wafers, making them suitable for unique applications where conforming to curved surfaces or rolling up when not in use are desired.  Printed electronics – using manufacturing processes more typically found in the graphic arts business – offers promise of a new, low-cost, approach to build displays and other electronic devices

About Dr. Hartney:
Dr. Mark Hartney joined USDC in June 2007 as Chief Technical Officer.  As CTO, Mark manages all technical activities of the USDC, including:  working with industry on the proposal and selection process of technical projects; management of project contracts; communication with government sponsors; chairing the USDC Technical Council; and all other activities involved with fulfilling the organization’s technical mission. 

Prior to this, Mark worked at Silicon Image, a semiconductor manufacturer in a variety of technical marketing and business development roles, and at dpiX, a display and sensor manufacturing company in similar roles. He is also a principal in Table Talk Consulting.

From 1992 to 1996, Mark worked in a variety of positions in Washington DC executing federal policy and managed projects on both semiconductor manufacturing and displays, at the Defense Advanced Research Projects Agency (DARPA) and the White House’s Office of Science and Technology Policy (OSTP).   Mark also previously held research and development positions at MIT Lincoln Labs and AT&T Bell Labs.

Mark is a graduate of MIT (B.S. and M.S.) and earned his doctoral degree at University of California at Berkeley, all in chemical engineering.  He has over 60 technical publications, 100 conference presentations and 4 issued patents.

About Dr. Hopkins:
Dr. Hopkins received BS and MS degrees from University at Buffalo (UB), and Ph.D. from Virginia Tech (VPI&SU) where his primary study was in megahertz-frequency power supplies using high-density packaging techniques. He is a Research Professor, Director of the Electronic Power and Energy Research Laboratory, and Associate Director of the Electronic Packaging Laboratory at UB, and an IEEE Senior Member and IMAPS Fellow. He chairs several power electronics packaging technical committees and authored over 70 journal and conference pubs. He also has over 15 years of industrial experience at GE’s and Carrier Air Cond. Companies’ R&D centers, and was visiting fellow at several national labs.

Abstract: "Reliability and Failure Mechanisms of Laminate Substrates with Plated Interconections-- the effect of Via Structure and Materials in a Pb-free World."
Though it has changed considerably in 50 years of electronic packaging, the plated through via (PTV) in it’s many forms remains the most common interconnection in 1st and 2nd level packaging, and it is still one of the most feared in terms of reliability.  The reliability concern results not only from the thermal expansion mismatch between copper and laminate materials especially at assembly reflow temperatures, but because the copper or laminate cracks that result are often impossible to detect visually or electrically.  Moreover, this dual concern of high stress and low detectibility is as true for today’s microvias and buried vias as for conventional through holes even though they have considerably different failure mechanisms and nominal cycles to fail.

This presentation uses current induced thermal cycling (CITC) test results to compare fatigue life and failure mechanisms for a wide range of plated via interconnections from large holes to microvias, and including the effect of structure, materials, hole making processes, surface finishes, Pb free assembly temperatures, and thermal cycle test temperatures.  The origin of PTV induced laminate failures such as “eyebrow cracks” and Pb free related delamination is also explored.  In addition to life data and failure analysis, CITC is used to produce high magnification video clips of actual via displacements and failure mechanisms during thermal cycling to further illustrate and compare the reliability challenges involved in laminate substrates with plated interconnections.

About Mr. Knadle:
Kevin Knadle is senior engineer at Endicott Interconnects Technologies in Endicott, NY, previously with the microelectronics division of IBM.    He has 24 years experience with reliability engineering and testing on all levels of electronic packaging.  He holds 13 US patents, and has authored a number of technical papers on PTV and solder joint reliability.    Kevin received his BS in Materials Science and Engineering from the MIT (1983), and MS in Mechanical Engineering from Binghamton University (1995.)

Abstract:
DARPA iMINT Center was established in September 2006 with a mission to establish science and technology for nanotube/nanowire/graphene-enabled microsystems. iMINT research studies will be reviewed with an emphasis on barrier coatings and flexible thermal ground planes. Barrier coatings are essential to protect organic light emitting diodes from moisture and oxygen attacks; such coatings can also make polymer packages hermetic. Atomic layer deposition (ALD) of alumina is a known barrier coating process. However, ALD alumina may crack under strains. A new molecular layer deposition (MLD) process has been developed to solve this cracking problem with enhanced mechanical toughness. The ALD/MLD barrier coatings also enable us to develop a flexible circuit board-based thermal ground plane (TGP). With nano-scaled features fabricated on evaporators and condensers, such a 1-mm thin TGP can achieve an effective thermal conductivity 100X better than copper’s. It is also expected to surv ive even under a 20-g acceleration condition.

About Dr. Lee:
Y. C. Lee is a Professor of Mechanical Engineering and the Director of DARPA Center on Nanoscale Science and Technology for Integrated Micro/Nano-Electromechanical Transducers (iMINT) at the University of Colorado - Boulder. He is also the Administrative Director of the Nanomaterials Characterization Facility. From 1993 to 2002, he had been the Associate Director of the NSF Center for Advanced Manufacturing and Packaging of Microwave, Optical and Digital Electronics (CAMPmode). Prior to joining the University, he was at AT&T Bell Laboratories, Murray Hill, New Jersey. Dr.  Lee's research focuses on the integration of MEMS and NEMS with microelectronic, optoelectronic and microwave devices.  Dr. Lee was an Associated Editor of ASME Journal of Electronic Packaging (2001-2004) and a Guest Editor for special issues on Packaging for Micro/Nano-Scale Systems for IEEE Transaction on Advanced Packaging (2003, 2005 and 2007). He is an ASME Fellow and has received the following awards:

Presidential Young Investigator (NSF, 1990); Outstanding Young Manufacturing Engineer Award (SME, 1992); Outstanding Paper Award (IEEE-ECTC, 1991); Outstanding Paper Award (ASME J. of Electronic Packaging, 1993); Honorable Mention Paper Award (IEEE Transactions on Advanced  Packaging, 2003); Meritorious Paper Award (GOMACTech-03); CU-ME Woodward Outstanding Mechanical Engineering Faculty Award, 2005-2006; and ASME Electronic and Photonic Packaging Division’s Mechanics Award in 2007.

CURRENT POSITION AND RELEVANT EXPERIENCE:
Dr. Leslie is the Chief Technologist for Powerex.  His responsibilities include new product and process development, leading government related R&D projects and advising/consulting in yield improvement and cost reduction efforts. For the past 5 years, Dr. Leslie has worked extensively in the development of high voltage, high temperature module design, packaging and characterization of silicon carbide devices.   He has also done extensive developement and evaluation of new power module thermal designs. He has also been active in the development of power semiconductor assemblies & subsystems for industrial and military applications that incorporate power semiconductor switches, heatsinks, gate drive circuits, temperature and current measurement capabilities. Dr. Leslie has also managed and been actively involved in custom and application-specific power semiconductor module package development and production for a wide variety of military, aerospace & industrial applications. For the past 25 years with the Westinghouse Research Center and Powerex, he has developed high voltage and high power silicon-based SCRs, diodes, static induction transistors and bipolar transistors.  He also has extensive experience in power device fabrication process development, yield improvement, cost reduction and manufacturing cycle time reduction. Dr. Leslie holds 2 US Patents and has authored 23 technical papers, 12 in the semiconductor field & 11 in the high power gas discharge laser field.

Abstract: "Benefits of Advanced Holographic Optics In Photovoltaic"
Although Prism Solar only makes an optical film, it is an optical film with the potential to revolutionize solar photovoltaics. Why? Because in conjunction with today’s proven silicon photovoltaic cells, Prism’s optical film can make solar energy competitive with conventional electricity.

This nearly miraculous transformation can be achieved by using the Prism Solar holographic optical film to guide sunlight to the surface of nearby solar cells. Within what looks like a traditional flat-plate PV module, strips of Prism film alternate with strips of traditional silicon solar cells. Where light is incident on the cells, it makes electricity in the normal way. Where light is incident on the film, it is guided sideways to the surface of the cells and converted to electricity. By this means, two-thirds of the expensive solar cells can be replaced by inexpensive Prism film without affecting the module efficiency.

About Mr. Lewandowski:
Richard P. Lewandowski, President and CEO of Prism Solar technologies, Inc. (PST):  PST is a Lake Katrine, New York early stage manufacturer of advanced holographic solar electric modules.  Mr. Lewandowski has over 25 years experience in the field of solar energy.   Founder and former CEO of SunWize Technologies, Inc., one of the largest PV distributors in North America.  Former Vice President of Technology, Besicorp Group, Inc.  Founder, past President and Board Director of the New York Solar Energy Industry Association.  Founder and past President of the Illinois Solar Energy Industry Association.  Former President of the ASES Chapter - Illinois Solar Energy Association.

Abstract: "Improving Microelectronic Wire Bonding: New Bonding Materials, Process Methods, and Microsensor Applications"
Fine wires have long been used to interconnect integrated circuits and microsystems. Modern thermosonic ball bonding processes reliably produce up to 30 Au bond loops per second. This presentation reports on contributions to accelerate the progress towards further miniaturized bonds with less expensive materials and improved reliability. For example, fast bonding wire assessment methods are presented based on sophisticated profile modifications for the main process parameters in combination with real-time signals of position and force recording during test bonds are made. These methods allow to effectively compare novel bonding wire types with respect to quantities related to process robustness, quality, and yield, significantly reducing the time requirement for such comparsions.

About Dr. Mayer:
Michael Mayer joined the faculty of the University of Waterloo, Ontario, Canada, in 2004. His research focuses on the detailed understanding of the physical mechanisms of electronic packaging processes for microelectronics and microsystems. Dr. Mayer received his diploma degree in Physics in 1994 and PhD degree in Technical Sciences in 2000, both from the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland. For his thesis he was awarded the ETH Medal in 2001. From 2000 to 2004 he was with Oerlikon Esec, Cham, Switzerland, where he was awarded the ESEC Inventor of the Year Award in 2003.  Michael co-authored more than 50 technical publications and eight patent applications, many of which have been awarded full patents in several countries.

Abstract: MEMS Packaging
Low cost and reliability are the main important factors for the successful commercialization of MEMS devices. It is possible to decrease the cost of the MEMS device by shifting from ceramic packages down to wafer level bonded MEMS. On the other hand, the ability to maintain the suitable environmental conditions either vacuum or inert gas inside the package of MEMS devices is the key for assuring high performances reliability. The pressure requirements of some MEMS hermetically packaged devices such as gyroscopes, resonators, IR bolometers and RF switches are very stringent in the range of 10-3 Torr. The most experienced and technically accepted way to keep constant the ambient of a hermetically sealed devices is the getter material, that is able to chemically absorb active gasses under vacuum or in inert gas atmosphere for the lifetime of the MEMS devices. Although the introduction of getter material in hermetically sealed MEMS packaging has been proved to be viable way to prevent performances degradations, modeling of packaging represent the key factor for a successful MEMS packaging design. In this talk, I will discuss the main factors that are critical in the attainment of desired vacuum, present a novel calculation model that enables the prediction of MEMS vacuum level after bonding and during the lifetime.

About Mr. Moraja:
Marco Moraja after graduating in Electronics in 1994, at the Polytechnic University of Milano, he spent one year period in a post university research activity in biochemical robotics screening systems at DIBIT Biotechnology Department of MIlano S. Raffaele Hospital. In 1995 he joined SAES getters as project engineer in R&D corporate laboratories. In 1998 he took the responsibility of the Vacuum system laboratory and lunching MEMS getter film basic research activities. From 2004 as Business Development Manager of the getter for MEMS Business Unit he took the responsibility of SAES getters MEMS products line. He authored and co-authored more than 20 technical and scientific papers together being inventor or co-inventor of more than 10 international patents, most of them directly related to MEMS applications.

Abstract: "Orthogonal Processing in Flexible Electronics"
In this talk we present a new patterning method, orthogonal lithography, that enables the processing of organic semiconductors in serial steps that are not otherwise possible. The ability to process more than one organic semiconductor without intermixing has long been desired but has remained impossible to date. The invented process makes use of new photoresists that can be processed in non-polar supercritical CO2 or fluorinated solvents that do not damage the organic semiconductors (in contrast to conventional solvents) yet enable pattern formation. The unusual properties of these non-polar solvents require these very special resists.  Both polymeric and molecular glass resists have been shown to work.  This process and the resist materials are expected to revolutionize the production of organic electronics.

About Professor Ober:
Christopher Kemper Ober is the Francis Bard Professor of Materials Engineering at Cornell University. After several years in industry at the Xerox Research Centre of Canada, Ober moved to Cornell as an Assistant Professor in 1986. His research is focused on lithography, patterning, the biology materials interface and control of surface structure in thin films. As a reflection of his contributions to lithography, Ober received the 2003 International Sematech Outstanding Contribution Award and in 2004 was honored with the Photopolymer Science & Technology Award. An Associate Editor of Macromolecules and the President of the IUPAC Polymer Division, he is the 2006 winner of the American Chemical Society Award in Applied Polymer Science and received a Humboldt Research Prize in 2007. In 2007, he also chaired the NSF Polymers Workshop.  Ober recently became Associate Dean of Research and Graduate Studies.

Abstract: "Current State of Understanding of Sn-whiskers:
It is well know that whisker formation can occur on devices made from electroplated Sn on Cu alloy lead frame packages.  Although there is no agreed upon atomistic model/s (theoretically or empirically based) for this effect, the majority of the researchers appear to be in agreement that compressive stresses in the Sn film provide the excess energy required to initiate the process that leads to the formation and growth of Sn-whiskers.  Beyond this, the theories diverge both in terms of the root cause/s that lead to compressive stresses and the mechanism/s responsible for relieving the compressive stresses and ultimately leading to whisker growth.  This paper will focus on what is known and not known relative to fundamental mechanisms of whisker growth, including the influence the statistical nature of whisker growth has upon fundamental understanding.  The talk will end with a review of the recently develop temperature humidity acceleration functions for whisker growth.

About Dr. Osenbach:
After receiving a PhD in Ceramic Science and Engineering from Penn State, John Osenbach joined AT&T Bell Labs in 1982.  John has been with AT&T, Lucent, and Agere Systems, and LSI Corp. his entire career.  He is current a Fellow in LSI Corp responsible for materials technology, he is also a Bell Labs Fellow.  The past 6 years he has primarily focused on packaging, both wire bonded and flip chip bonded, ICs produced in Cu/Low K/Ultra-low K technologies and the development of lead free package technology.  His primary interest is in the development of the materials and designs required for high volume manufacture of reliable Cu/low K-wire bonded- and flip chipped- lead free packages.  The previous 10 years of his career were spent developing reliable hermetic and non-hermetic InP-based optoelectronic packages.  His primary focus during this time was the development of materials and process technologies for silicon optical benches, high speed WDM optical packages, reliable WDM o  p!
tical non-hermetic packages, and MEMS based optical cross connect systems.  The first 10 years of his career were spent developing processes and materials for high voltage, high speed bipolar, CMOS, and BiCMOS integrated circuit technologies.  He primarily focused on passivation, metallization, epitaxy and the reliability thereof. He has authored and co-authored more than 80 papers and has been issued 36 patents, with an additional 25 patents pending.  He was a past associate editor of the Journal of the Electrochemical Society program chair for the dielectrics division of the electrochemical society, has organized and chaired optoelectronic packaging conferences, and has taught courses on reliability physics of optoelectronic devices at the optical fiber conference.  He is also committed to his community believing that giving back to society is both an integral part of building and maintaining a strong society as well as being required for personal growth.  To this end, John has been school board member, and was a founding member of the board of Service Access Management of Berks county PA (a non-profit that provides services and information to people with mental health, mental retardation, and physical impairment issues).  He currently is a Governor appointed member of the PA developmental disability.

Abstract: "Electrical, Mechanical and Reliability Performance of Nano-Micro-Filled Conducting Adhesives for z-axis Interconnections"
Greater I/O density at the die level, coupled with more demanding performance requirements, is driving the need for improved wiring density and a concomitant reduction in feature sizes for electronic packages.  Alternatives to the traditional plated through hole are required for high frequency and high density interconnect applications. One method of extending wiring density is a strategy that allows for metal-to-metal z-axis interconnection of sub-composites during lamination to form a composite structure. There has been increasing interest in using electrically conductive adhesives as interconnecting materials in the electronics industry.  Conductive adhesives are composites of polymer resin and conductive fillers. Metal–to-metal bonding between conductive fillers provides electrical conductivity, whereas a polymer resin provides better processability and mechanical robustness.   Conductive adhesives have been used to fill vias in sub-composite structures, and form conductive joints to metal planes during lamination to adjoining circuitized cores. Reliability of the conductive joint formed between the conductive adhesive and the metal surface to which it is mated is of prime importance.

About Dr. Poliks:
Mark D. Poliks is Director of Research and Development at Endicott Interconnect Technologies, Inc., (EI).  He is also Technical Director of the Binghamton University based Center for Advanced Microelectronics Manufacturing (CAMM) and Research Professor of Chemistry, Materials Science and Engineering at Binghamton.  He has authored over one hundred technical papers and invited presentations and holds thirty-five US patents.   He is chair of the materials and processing committee for the ECTC, and a member of the USDC technical council, an Associate Editor of the ASME “Journal of Electronic Packaging”, a member of the American Chemical Society, the Materials Research Society and the IEEE/CPMT. 

Harnessing solar energy by direct conversion to electricity using photovoltaic (PV) cells formed by inexpensive and sustainable materials and manufacturing techniques is a challenge. The single-or multicrystal silicon solar cells because of energy intensive fabrication methods and thin film amorphous silicon and CdTe, Cu(InGa)Se2 heterojunction solar cells which use complex processes for high efficiency and stability are still to rival the grid electricity in cost. New concepts and solar cell designs that challenge the conventional p-n junction approach and  radically different technologies for the solar cell fabrication are being intensively researched. The third generation solar cells will be made over flexible platforms and will be based on semiconductor nanocrystals, polymeric semiconductors and hybrid of both.  The flexible solar modules not encumbered by bulky glass and large amount of specially processed conductive coatings can be unobtrusively integrated with many appliances without amending the form factor. Nanotechnology approach to flexible solar cells enables spray coating, direct printing, and electroplating to produce semiconductor nanoparticles that have the potential to dramatically reduce cost, increase throughput and enable high yields in a roll to roll production line. Semiconductor nanocrystals show the quantum optical properties different from bulk material, thus harvest a wider range of solar radiation and produce more photo-charges contributing to higher efficiency. In bulk heterojunction design of solar cells, these nanoparticels mixed with semiconducting polymers have the potential for efficient exciton dissociation and charge separation. This presentation would review underlying scientific principles and emerging technologies that reflect a paradigm shift in the design and fabrication of flexible solar modules.

About Alok Rastogi:

Dr. Alok Rastogi is a Research Professor in the Electrical and Computer Engineering Department at Binghamton University, State University of New York, Binghamton. He has held several leadership positions in projects directed towards the development of cost effective solar photovoltaic energy conversion technologies and has made specific contributions to the development of thin film heterojunction and nanocrystalline solar cells and novel photovoltaic materials and processes. He has actively fostered private industry participation in solar cells and achieved technology sharing agreement with EcoSolar in production of CdTe solar Cells; provided technology support in validation of solar cell test protocols; and has participated in the coordinated European Photovoltaic Solar Energy Projects. He has published over 155 research papers in technical journals of which more than 70 research papers are in the area of thin film photovoltaic solar cells, and nanoscaled materials for photovoltaics. Focus of his current research is on the nanocrystalline semiconductors and hybrid solar cells on flexible platform and ultracapacitors for energy storage based on nanocomposite conducting polymers. His other researches are on wide band-gap oxide semiconductors and multiferroic thin films for transparent electronics and spintronics.

Abstract: "A Proactive Approach to Improving Environmental Performance"
The member companies of iNEMI have worked together since 1996 in roadmapping and closing gaps related to the environment.  The initial work was focused on high volume consumer applications and dealt primarily with the changes required to comply with the EU RoHS regulations including technology evaluations, supply chain readiness, as well as data reporting requirements.  Over time the cooperative activities took on the more stringent needs of the mission critical applications.  This area continues to be the focus of a number of today’s iNEMI projects.   

With environmental regulations multiplying on an international basis, industry is realizing that a more strategic approach is needed.  As a first example of this change in attitude, iNEMI’s efforts on BFR-free electronics will be discussed.  Finally we will review our plans to start a new initiative on sustainability.  This effort will begin with a summit meeting that brings together thought leaders from industry and academia to develop the outline of a thrust that has the potential to become a major part of our future collaborative agenda.  This is a subject that will increasingly impact our entire industry as well as the global society.  

About Mr. Richardson:
Charles E. Richardson is the Director of Roadmapping for iNEMI (International Electronics Manufacturing Initiative) and has been with iNEMI for 6 years. Chuck received the BSEE degree from The Ohio State University and worked as an analog / digital electronics, metrology systems Design Engineer for 7 years before transitioning into Manufacturing Engineering and finally Manufacturing Senior Management. He has held Manufacturing / Mfg. Engineering Management positions at companies including Esterline Corp., Cooper Industries, Micro Industries, Intergraph Corp. and SCI. Prior to iNEMI, he most recently served as Corporate Engineering Manager at SCI in Huntsville, Alabama for 3 years where he was responsible for developing and maintaining the world wide architecture for advanced process development and new product introduction - including SCI corporate roadmapping and customer roadmapping liaison.

Chuck has been a frequent speaker for various companies and organizations on surface mount processing and associated business issues - including the SMTA, IPC, iNEMI, EIA, SMTAI, APEX and Productronica.

Chuck has been active in the SMTA starting in 1983, serving as a National SMTA Director for 9 years. He also started the Ohio Valley Chapter and aided in the resurrection of the Tennessee Valley Chapter. During the early years of SMTA, he toured the country participating in various SMTA related shows, presenting educational information and furthering the technology's growth. Chuck is also a long time member of the IEEE.

Abstract: High Temperature Electronics

Significant attention has been focused on the development of the micro-machining techniques MEMS devices, but the packaging of the devices to interconnect to the outside world and perform in the specified environment has always been the poor relation. Packaging can account for up to 80% of the MEMS module costs and there is interest in driving out the packaging costs whilst maintaining or improving on the device performance and sensitivity.

Several microsystem devices must be operated in a vacuum for optimum performance, and the cost of the vacuum encapsulation can dominate the cost of the finished product. Traditionally, the individual microsystem devices are packaged in metal or ceramic packages. Wafer level packaging is growing for many applications, where vacuum tight micro-cavities are produced between glass and silicon wafers, which are then individually diced. This presentation will focus on the manufacturing challenges for MEMS packaging in high and low volume industries.

About Steve Riches:

Steve Riches joined Micro Circuit Engineering in May 1999, after 16 years at The Welding Institute, where he worked on assembly and packaging techniques for microelectronics and laser processing, including work on copper wire bonding and assessment of die attach materials.

He has worked as Business Development Manager for GE Aviation Systems – Newmarket/Tewkesbury (formerly Micro Circuit Engineering), focusing on new product development for ruggedised displays, MEMS packaging and high temperature electronics. He is currently running several UK Technology Strategy Board projects in these areas

Abstract: "Advanced Packaging for Silicon Carbide Power Devices"

Emerging silicon carbide (SiC) power devices offer improved efficiency, faster switching and operation at higher temperatures compared to industry workhorse, silicon power devices. SiC power devices also require advanced packaging in order to maximize performance benefits. This presentation will give an overview of recent activities at GE Global Research in SiC packaging for the next generation of power conversion applications.

About Ljubisa Stevanovic:

Ljubisa Stevanovic received his B.S.E.E. degree from Belgrade University in Serbia in 1988, and M.Sc.E.E. and Ph.D. degrees in Power Electronics from California Institute of Technology, Pasadena, California. He has been with GE Global Research Center, Niskayuna, New York, since 1993. In his current role as Chief Engineer for Advanced Technologies, Dr. Stevanovic leads development of Silicon Carbide power devices, circuits and packaging for high-performance power electronic systems.

Abstract: "Emerging Nanotechnology Approaches for Solar Photovoltaic Cells over Flexible Platform"
Harnessing solar energy by direct conversion to electricity using photovoltaic (PV) cells formed by inexpensive and sustainable materials and manufacturing techniques is a challenge. The single-or multicrystal silicon solar cells because of energy intensive fabrication methods and thin film amorphous silicon and CdTe, Cu(InGa)Se2 heterojunction solar cells which use complex processes for high efficiency and stability are still to rival the grid electricity in cost. New concepts and solar cell designs that challenge the conventional p-n junction approach and  radically different technologies for the solar cell fabrication are being intensively researched. The third generation solar cells will be made over flexible platforms and will be based on semiconductor nanocrystals, polymeric semiconductors and hybrid of both.  The flexible solar modules not encumbered by bulky glass and large amount of specially processed conductive coatings can be unobtrusively integrated with many appliances without amending the form factor. Nanotechnology approach to flexible solar cells enables spray coating, direct printing, and electroplating to produce semiconductor nanoparticles that have the potential to dramatically reduce cost, increase throughput and enable high yields in a roll to roll production line. Semiconductor nanocrystals show the quantum optical properties different from bulk material, thus harvest a wider range of solar radiation and produce more photo-charges contributing to higher efficiency. In bulk heterojunction design of solar cells, these nanoparticels mixed with semiconducting polymers have the potential for efficient exciton dissociation and charge separation. This presentation would review underlying scientific principles and emerging technologies that reflect a paradigm shift in the design and fabrication of flexible solar modules.

About Dr. Alok Rastogi
Dr. Alok Rastogi is a Research Professor in the Electrical and Computer Engineering Department at Binghamton University, State University of New York, Binghamton. He has held several leadership positions in projects directed towards the development of cost effective solar photovoltaic energy conversion technologies and has made specific contributions to the development of thin film heterojunction and nanocrystalline solar cells and novel photovoltaic materials and processes. He has actively fostered private industry participation in solar cells and achieved technology sharing agreement with EcoSolar in production of CdTe solar Cells; provided technology support in validation of solar cell test protocols; and has participated in the coordinated European Photovoltaic Solar Energy Projects. He has published over 155 research papers in technical journals of which more than 70 research papers are in the area of thin film photovoltaic solar cells, and nanoscaled materials for photovoltaics. Focus of his current research is on the nanocrystalline semiconductors and hybrid solar cells on flexible platform and ultracapacitors for energy storage based on nanocomposite conducting polymers. His other researches are on wide band-gap oxide semiconductors and multiferroic thin films for transparent electronics and spintronics.

Abstract: "High Temperature Electronics"
The requirement to install electronic power and control systems in high temperature environments has posed a challenge to the traditional limit of 125oC for temperature exposure of electronics systems. The leap in operating temperature to above 200oC in combination with high pressures and vibrations means that different semiconductors, passives, circuit boards and assembly processes will be needed to fulfil the target performance specifications. 

The reliability data for the operation of electronics systems from -55oC to +125oC do not apply to the operation of electronics at higher temperature, as the failures may be more dominated by diffusion and creep rather than fatigue. The basis of the approach being pursued in this work is to model the mechanical, electrical and thermal characterisation and microstructural analysis of representative high temperature test structures.

This work forms part of the UPTEMP project has been set-up with support from UK Technology Strategy Board and the EPSRC.

About Mr. Riches:
Steve Riches joined Micro Circuit Engineering in May 1999, after 16 years at The Welding Institute, where he worked on assembly and packaging techniques for microelectronics and laser processing, including work on copper wire bonding and assessment of die attach materials.

He has worked as Business Development Manager for GE Aviation Systems – Newmarket/Tewkesbury (formerly Micro Circuit Engineering), focusing on new product development for ruggedised displays, MEMS packaging and high temperature electronics. He is currently running several UK Technology Strategy Board projects in these areas.   

Abstract:

The Vehicles Technologies Program (VTP) at the Department of Energy is tasked with the development of energy efficient and environmentally friendly highway transportation technologies to decrease America’s dependence on foreign oil.  Through the FreedomCAR and Fuel Partnership, VTP partners with National Laboratories, major oil companies, utilities and automotive manufacturers to examine pre competitive, high risk research needed to develop the component and infrastructure technologies necessary to enable future vehicles.  The Partnership conducts technology road mapping, determines technical requirements and suggests R&D priorities, as well as monitors the activities necessary to achieve the Partnership’s research goals.  The Partnership has developed a set of requirements for electrical drive train components to facilitate the development of hybrid, plug in hybrid and ultimately fuel cell vehicles.  These requirements address cost, reliability, power density, and specific p  o!
wer for the traction drive system as well as for inverters, DC to DC converters, and electric motors.
There is a growing move towards higher temperature operation of electronics in vehicles to eliminate separate cooling loops and reduce cost.  It is desired to operate high current, high power devices with water/ethylene glycol coolant at temperatures of 105ºC and beyond.  Imperative to achieving these goals is electronic packaging.  New methods of housing high power devices are needed which reduces thermal impedances in the packaging, allowing higher heat dissipation.  New topologies and packaging innovations at the system as well as the subsystem level are wanted to reduce parasitic impedances and inductance and mitigate the need for bulky bus capacitors. 
Breakthrough packaging advances at the component, module, subsystem, and system level are necessary to achieve the VTP targets.  This will aide in the rapid deployment of technologies necessary for the electrification of vehicles to reduce the nation’s dependence on imported oil and minimize vehicle emissions in the future.

About Susan Rogers:

Susan Rogers is the manager of the Advanced Power Electronics and Electrical Machines Research & Development activities for the Vehicle Technologies Program at the Department of Energy. She also managed the recently completed $12.5 million Advanced Heavy Hybrid Propulsion Systems research and development activities. Susan has twelve years of experience managing transportation technologies for the DOE, including energy storage, fuel cells, and hybrid propulsion systems.  Prior to working at DOE, Susan worked for the Department of the Navy as the program manager for the electrical systems and components for the SEAWOLF submarine.  Susan holds degrees in electrical engineering and biology from The Pennsylvania State University and Temple University.

Abstract: "Active Microstructure Cooling for High Heat Flux Applications"
High-power-density applications such as gamer PCs, high-end projectors and LED displays have essentially maxed out the ability of conventional cooling methods to keep system temperature levels within acceptable operating limits, indicating the need for a “next-generation” approach. Multiple heat pipes, vapor chamber/fan heat sink hybrids, and other optimized cooling methods, can only delay, at best, the inevitable need for more efficient cooling as higher-performance applications continue to generate greater levels of thermal energy. 

On the other hand, liquid cooling systems (LCS) have been making major strides in recent years for meeting the cooling demands of the next generation high performance applications. LCS have been around for several years, but were limited in their general market acceptance due to issues like leakage and other reliability problems. However since the advent of improved technology and manufacturing techniques, tens of thousands of LCS have experienced up to several years of operation with zero field failures. This has led to growing market acceptance of liquid cooling by several leading OEMs, as evidenced by a slew of niche products in the gamer PC market which are now liquid cooled.

In this presentation, examples of two applications of microstructure liquid cooling systems will be discussed.  The first one is a gamer PC application for cooling a CPU and two GPUs, with the total power upto 450 W.  The second example is a LCS for a high brightness LED cooling, for a display device.      

About Dr. Upadhya:
Dr. Girish Upadhya is the Director of Applications Engineering at Cooligy, a subsidiary of Emerson Network Power.  Prior to Cooligy, Girish served at Apple Computer for where he was responsible for the thermal design of various award winning products such as iMac, G-4 Cube, iBook, G-4 Powerbook, and the G-4 Power Mac.  Girish received his Ph. D. from The University of Alabama, and his Bachelor’s and Master’s from Indian Institute of Technology, Kanpur and Madras, respectively.  Girish has authored or co-authored more than 50 technical publications, and more than 10 issued patents.

Abstract: Hygroscopic Stress Effects on MEMS Devices and Packages

A packaged MEMS device may experience offset shifts and reliability issues due to the hygroscopic stress from plastic material moisture absorption and thermo-mechanical stress from CTE mismatch.  Material characterizations, modeling and simulation to minimize the stress-induced issues is very critical for high-performance MEMS sensors. In this presentation, several types of MEMS plastic packaging materials are characterized with an emphasis on hygroscopic material properties such as diffusivity, moisture concentration and coefficient of hygroscopic swelling at different temperatures.  A new method of accurate modeling of the hygroscopic stress effects through finite element analysis (FEA) will also be introduced.   Finally, improvement of modeling accuracy by correlating FEA models with measured package material properties and warpage will be presented.  Using the reduced-order MEMS sensor and package Interaction (MPI) model, device offset performance is simulated, optimized and correlated with actual data collected for a newly developed 3-axis accelerometer.

About Xin Zhang:

Xin (Sam) Zhang is a senior MEMS design engineer at Analog Devices’ Micromachined Products Division in Cambridge, MA.  He designs MEMS accelerometers, microphones, optical switches and other products.  He together with Dr. Michael Judy designed the MEMS structures of the ADXL330 (the 3-axis accelerometer that enables the Nintendo Wii).  In addition to designing MEMS sensors, he is also an expert in modeling MEMS packages and sensor-package Interactions.  He has about 10 U.S. patents pending or awarded.  He was the recipient of the Best Paper Award at the IEEE ITHERM 2006 Conference and one of the recipients of ADI’s Award for excellence in product development.  He received a B.S. in Precision Engineering and a B.A. from Tsinghua University in Beijing China. He has an M.S. in MEMS design from the George Washington University in Washington D.C.